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<!doctype html>

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<title>CodeMirror: Verilog/SystemVerilog mode</title>

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<a href="http://codemirror.net"><h1>CodeMirror</h1><img id=logo src="../../doc/logo.png"></a>

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<ul>

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<li><a href="../../doc/manual.html">Manual</a>

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</ul>

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<ul>

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<li><a href="../index.html">Language modes</a>

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<li><a class=active href="#">Verilog/SystemVerilog</a>

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</ul>

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</div>

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<h2>SystemVerilog mode</h2>

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// Literals

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1'b0

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1'bx

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1'bz

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16'hDC78

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'hdeadbeef

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'b0011xxzz

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1234

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32'd5678

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3.4e6

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-128.7

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// Macro definition

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`define BUS_WIDTH = 8;

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// Module definition

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module block(

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input clk,

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input rst_n,

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input [`BUS_WIDTH-1:0] data_in,

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output [`BUS_WIDTH-1:0] data_out

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);

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always @(posedge clk or negedge rst_n) begin

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if (~rst_n) begin

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data_out <= 8'b0;

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end else begin

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data_out <= data_in;

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end

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if (~rst_n)

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data_out <= 8'b0;

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else

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data_out <= data_in;

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if (~rst_n)

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begin

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data_out <= 8'b0;

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end

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else

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begin

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data_out <= data_in;

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end

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end

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endmodule

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// Class definition

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class test;

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/**

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* Sum two integers

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function int sum(int a, int b);

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int result = a + b;

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string msg = $sformatf("%d + %d = %d", a, b, result);

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$display(msg);

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return result;

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endfunction

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task delay(int num_cycles);

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repeat(num_cycles) #1;

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endtask

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endclass

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</textarea></div>

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var editor = CodeMirror.fromTextArea(document.getElementById("code"), {

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lineNumbers: true,

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matchBrackets: true,

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mode: {

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name: "verilog",

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noIndentKeywords: ["package"]

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}

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});

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</script>

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<p>

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Syntax highlighting and indentation for the Verilog and SystemVerilog languages (IEEE 1800).

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<h2>Configuration options:</h2>

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<ul>

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<li><strong>noIndentKeywords</strong> - List of keywords which should not cause indentation to increase. E.g. ["package", "module"]. Default: None</li>

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</ul>

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</p>

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<p><strong>MIME types defined:</strong> <code>text/x-verilog</code> and <code>text/x-systemverilog</code>.</p>

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</article>

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